There's Chisel (Scala based) the LowRisc team from Berkeley are using[1]. It can output Verilog and also compiles to cycle accurate simulators.

There's also PSHDL from Karsten Becker[2] at TUHH. It's immature and seems to be focused on teaching at the moment.

[1] https://chisel.eecs.berkeley.edu/ [2] http://blog.pshdl.org/

Hi, just a quick correction - the Berkeley RISC-V team are not one and the same with the lowRISC team. We collaborate with them, and we have Krste on our technical advisory board. We are of course also using Chisel though.