No, it's just all of the device models. Even the OSS tools take up almost 20 GB of space once you get all of the suppported device models which is not many compared to what Vivado supports.

Why not both? Look at the installables from Cadence, they are full of redundant garbage, broken rpaths, etc. Tools that don't even need to support devices have 5-8GB compressed installables with 12-20GB of on disk space being taken up.

Horribly broken installers and a mess of environment variables needed to get the software to even run.

As someone who actually worked for one of the largest FPGA consumers in the world, Xilinx didn't benefit at all from the community and hobbyist uptake. It was just an unnecessary expense and distraction that got in the way of their core mission. Around 5-10 companies make up around 70% of all FPGA silicon sales and the single largest end user is the U.S. Government and its customers (NATO members, Israel, Australia, Japan, South Korea, etc.). Now that cloud took off, FPGAs are somewhat more used in cloud deployments but usually as a stopgap measure until an ASIC can be developed. And putting the lines on the football field has finally stopped being one of the largest consumers because the broadcasters finally learned that they can load new programming onto the FPGAs instead of just ordering new hardware every time something changes.

They will notice their mistake once the hiring pool dries up.

In the long run they will be replaced by more competitive companies like Efinix.

> No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.

You have absolutely no idea what an ASIC costs compared to a FPGA. A FPGA that can compete with a tinytapeout chip costs a few dollars at most in extremely low quantites. Something high performance would need probably TSMC 12nm or similar at a minimum. At that point, you're talking $1M+ between licensing fees and direct costs to just go on a shuttle. If you want to make your own higher volume run or can't wait for shuttle spot, you're looking easily $5-10M minimum for your first 6 wafers. Comparatively, FPGAs competitive with TSMC 12nm run from a few hundred dollars up to several thousand dollars each. So for low volume, they're very competitive.

But ShotSpotter doesn't actually work (almost every alert is a false positive). So what value would this add?

No totally, I can't imagine it either, I was just trying to give it a charitable assumption.

Both SystemVerilog and VHDL have AMS extensions for simulating analog circuits. They work pretty well but you also pay a pretty penny for the simulator licenses for them.

I use AI for side projects because Google gives me a stupid large number of tokens that refresh every 6-24 hours on my existing $10/mo Google One plan. I see it as my civic duty to help increase their costs by producing slop that I generally throw away anyways because it doesn't actually work after it gets generated.

At work, I was told to use AI but it doesn't actually work for anything that I couldn't have handed off to a brand new undergraduate intern. So I use it for things that I don't care about then go spend twice as long rewriting what it output because it made the task longer by being wrong.

In my systems, I just go to an error log that gets posted to a Slack channel then go to the the log file and grep for full message that got dumped to Slack. That then gives me everything that happened before and a state dump after. That state dump can be given to a program to tell us if any state errored and what happened before tells us what the expectation was and what the precise error was. Using a LLM would just be slower and more expensive for this.

I can't get an LLM to properly handle analyzing a single 200K+ line log without making things up so whatever anyone is saying about this "working" is probably a lie.

Heavy rail and light rail costs are very comparable unless you want to bury them. But it doesn't matter which you bury, they still cost about the same.

I also live in Chicago but unlike you, I have musculoskeletal issues that can be minor to the point of not noticing or to the point of it being painful to walk more than 2-3 blocks at a time. So doubling the distance between blocks would be the difference between me being able to use the bus and me needing to drive or use the far more expensive for taxpayers paratransit service.

And beyond that, the 6% of average time savings seen in studies of similar systems would be about the same improvement as adding curb bump outs which would save the bus time by not needing to repeatedly merge back into traffic. And that work is already happening across the city without inconveniencing anyone or causing users with disabilities from being discriminated against by armchair urban planners.