What kinds of optimizations could be available to a system that can integrate a semantic and systematic understanding of a chip, microarchitecture and high-level compiled languages on top of that?
I know we have e.g. VHDL but to marry that to a high level language compiler seems like it would open some new doors (maybe this has already been done and I’m just not aware).
Compilers have had detailed pipeline and memory hierarchy models available for decades. This is not a new thing in LLVM, the new thing is a language for describing a pipeline (which replaces an older description language).
Instruction generation and scheduling optimizations primarily.
I don't know if much higher level optimization is done, possibly some cache blocking? I don't think the limitation is the hardware description available so much as actually using that to make worthwhile optimizations.
Going the other direction, it might allow better optimizations of microarchitectures for known workloads by allowing description and simulation of alternative designs at a high level of abstraction.
I know we have e.g. VHDL but to marry that to a high level language compiler seems like it would open some new doors (maybe this has already been done and I’m just not aware).