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>Using a three-dimensional chip design Intel plans to shrink that even further over the next couple of years, to 22nm and then 14nm, and sell chips that beat the competition on both energy-efficiency and performance.

/facepalm.

The rest is pretty good, though, I think.



What is wrong with that statement? Intel is using a new 3D Tri-Gate Transitor tech for 22nm & have plans for 14nm in the future.


Pretty much everyone outside Intel thinks FinFETs should not be called 3D, since 3D was already used to refer to die stacking.


Not to mention that chips are already 3D with multiple metal layers.


It makes it sound as though you need 3D to shrink the chips. I don't think that's the case. I don't like calling a 3D component a 3D chip design, either.


What's wrong? I can't see anything except extra dash in "energy efficiency"




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